A via is typically used to route a signal between two layers on a printed circuit board (PCB) referred to herein as “signal layer transition.” PCBs that contain vias commonly have four or more metal layers and may be composed of flame retardant 4 (FR4) material. In a typical four-layer board, for example, two layers are used for routing, and two for power and ground. Complex boards may exceed forty layers, with several power planes and numerous ground and routing layers. The thickness of PCBs may vary, but typically falls between 0.060 inches and 0.250 inches. The thickness of a board is generally dictated by the number of layers required to provide adequate power delivery, plane capacitance, ground references, shielding, desired trace impedance and convenient routing.
As illustrated in FIG. 1, circuit board 10 includes twelve layers (12-26). Representatively, via 30 provides a signal layer transition between, for example, micro-strip layer 12 and a strip line metal layer 16 of circuit board 10 The plated-through hole (PTH), a common means of implementing a via, is formed during PCB fabrication by first mechanically drilling a hole completely through the board following lamination, then plating the walls of the hole with copper or another conductor. This forms a tubular or solid conductive barrel that serves as a continuous electrical path through the board's entire thickness, connecting any metal layers or traces that abut the barrel.
A shortcoming of a PTH via is that its electrical behavior depends on which signal layers transit through its barrel. A through-board via, a PTH that passes a signal completely through the board to an opposite side of the board, can typically be designed to be absent any pronounced resonance, though it will contribute a small amount of loss and reflection of a very broad range of frequencies. As illustrated in FIG. 1, PTH via 30 provides a signal layer transition that is less than a thickness of the board referred to herein as a “short layer transition.” For example, a PTH used for a short layer transition, or perhaps only 0.010 inches of a 0.092 inch thick board, as shown in FIG. 1, results in a significant portion of its length (28) that does not carry the direct signal between layers referred to herein as “via stub.” As illustrated in FIG. 1, the unused length of PTH via 30 constitutes via stub 28 that exhibits a strong frequency-dependent behavior as signals approach its stub resonance frequencies.
The high frequency resonance exhibited by via stubs in PCBs is a common problem. Stub resonance is a well-known phenomenon in which any signals that traverse layers in a circuit board through a via possessing a stub are affected by the inherent passive resonance exhibited by the via stub. The resonance falls at frequencies dictated by the local geometry and composition of the PCB. This effect can dramatically reduce the fraction of energy that reaches the intended receiver, while increasing reflections toward the transmitter. Via stubs can also increase the parallel-plate mode conversion effect that plays a role in board resonance and via-to-via crosstalk.
Furthermore, via stub effects are becoming increasingly problematic as data rates used in circuit boards increase to the multiple gigabit/second (gb/s) range, and significant signal frequency spectral content approaches the resonance frequencies of their stubs. High reflection and low transmission through vias possessing stubs is a principal barrier to further increases in data transmission speed on circuit boards. Currently, there are no economical, straightforward methods to mitigate the via stub in many common via configurations, which may include ordinary open field layer transitions, or vias used to attach integrated circuit packages, chipset sockets or connectors.
Current techniques of dealing with stubs cannot be applied using processing technology currently available in many high volume manufacturing (HVM) circuit board production facilities. Several methods have been developed to mitigate the via resonance effect and to otherwise minimize the effects of a via's electrical parasitics. These methods may include adjusting the size and shape of the pad and anti-pad of the via or the size of the drilled hole. They may also include back-drilling and blind and buried vias. However, many of these methods require additional processing operations that are not available in HVM processes.